1. Field of the Invention
The present invention relates to a planarizing method of an object surface or a deposited film, especially relates to a planarizing method of a surface of a substrate or the like, or a film deposited on a substrate, which is used during manufacturing a magnetic device, a semiconductor device or the like.
2. Description of the Related Art
In recent years, more integrations of a magnetic device, a semiconductor device and so on have proceeded. For example, more integration of a thin-film magnetic head for reading/writing data has actively proceeded as well as higher performance, on demand for more improvement in areal recording density in the magnetic recording technique.
Most of the conventional manufacturing methods of such devices have a forming process of a predetermined element, by depositing a thin-film on a substrate and then by patterning the deposited film. Such a thin-film process meets the integration of the device by, for example, providing a microscopic width of the formed thin-film pattern with high accuracy. Here, a planarizing process is significantly important as well as the patterning process.
The planarizing process is a process for eliminating or reducing the variation in thickness or the step on the surface of the film deposited on the substrate. As a conventional technique of the planarizing process, there is, for example, an etch-back method. The etch-back method is a widely-used technique in which a resist, a spin-glass (SOG) or the like is applied so as to wholly cover the thin-film pattern formed on the substrate, and then the surface of the applied resist, SOG or the like is planarized by using an etching or a chemical mechanical polishing (CMP).
Further, as a means for resolving the negative effect of the steps, Japanese Patent Publication No. 03-261126A describes a forming method of gate electrodes of GaAs field-effect transistors (GaAs FET) in which a resist film pattern is formed with high accuracy to avoid the increase in gate length or the breaking of the formed gate electrode. Generally, a resist film pattern formed over a step portion has a tendency to become thicker around the step. As a result, it becomes difficult to perform an appropriate exposure to the whole resist film pattern. As a measure against this problem, the above-described forming method has a process to expose the resist film on the step portion separately in order to appropriately expose the whole resist film pattern.
However, even in this conventional technique, there has been a problem that a distribution or variation of film thickness in the resist film occurs when applying the resist, and thus, the distribution or variation of film thickness in the planarized film remains even after performing the planarizing process.
For example, in the case of planarizing a step by using the above-described etch-back method, under the presence of the distribution or variation of film thickness in the resist film as a buffer layer, it is significantly difficult to reduce the step within the amount of the distribution or variation. Further, in the case of planarizing a deposited film on a predetermined area of the substrate, the distribution of film thickness in the applied resist film occurs in this area when applying the resist. Therefore, it is also significantly difficult to suppress the distribution of film thickness in the planarized film within the amount of the distribution of film thickness in the applied resist film.